[Libre-soc-dev] Unexpected clock connexions.
Jean-Paul.Chaput at lip6.fr
Sat Jun 5 13:41:06 BST 2021
On Sat, 2021-06-05 at 13:17 +0100, Luke Kenneth Casson Leighton wrote:
> i've added the dummy (fake) PLL to experiments10_verilog using nsxlib with
> the (fake) PLL cell
> also worked out how to fix the nsxlib error "jtag_tck_from_pad" is not a
> clock tree error
> i am however experimenting tracking down the right H-Tree clock for use in
> ls180Conf, it's probably
Nono. That's correct. It is really 'core.por_clk'.
When building a complete chip *from* a core, say "ls180",
the core2chip procedure creates two levels of additional
1. corona, which instantiate the core model, and it's
instance name will be 'core'.
2. The chip level, which instantiate *only* the corona
and all the I/O pads.
However, the P&R is done not at ls180 model level, but
at corona model level. So, as "por_clk" is an *internal*
signal of ls180 (comes out from the PLL) and have no
"representative" at corona level, we must reach it through
the path : 'core.por_clk' (path rooted in corona model,
one instance 'core', which is the ls180).
> also, is it likely that "coresync_rst" also has to be added?
Depends. It is in the "middle range". Many sinks, but maybe
not that much to need an H-Tree. If it needs a low skew, maybe.
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
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