[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

i've added the dummy (fake) PLL to experiments10_verilog using nsxlib with
the (fake) PLL cell
https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=a876c5dd61a53230de74b2ca2900e0e09490da95

also worked out how to fix the nsxlib error "jtag_tck_from_pad" is not a
clock tree error
https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=c24e13b1078fa2d358d6b7f91cfd96905c100769

i am however experimenting tracking down the right H-Tree clock for use in
ls180Conf, it's probably

    ls180Conf.useHTree('por_clk)

not

    ls180Conf.useHTree('core.por_clk')

also, is it likely that "coresync_rst" also has to be added?

l.