[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 5 13:17:59 BST 2021
i've added the dummy (fake) PLL to experiments10_verilog using nsxlib with
the (fake) PLL cell
also worked out how to fix the nsxlib error "jtag_tck_from_pad" is not a
clock tree error
i am however experimenting tracking down the right H-Tree clock for use in
ls180Conf, it's probably
also, is it likely that "coresync_rst" also has to be added?
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