[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

(coriolis2)lkcl at fizzy:~/coriolis-2.x/src/coriolis$ git diff
diff --git a/crlcore/src/ccore/toolbox/NamingScheme.cpp
b/crlcore/src/ccore/toolbox/NamingScheme.cpp
index e547cdf9..1f8af188 100644
--- a/crlcore/src/ccore/toolbox/NamingScheme.cpp
+++ b/crlcore/src/ccore/toolbox/NamingScheme.cpp
@@ -61,6 +61,7 @@ namespace CRL {
   // VHDL reserved keywords (scalar).
     if (loweredName == "in"   ) return "in_v";
     if (loweredName == "out"  ) return "out_v";
+    if (loweredName == "ref"  ) return "ref_v";
     if (loweredName == "inout") return "inout_v";
     if (loweredName == "true" ) return "bool_true";
     if (loweredName == "false") return "bool_false";

---
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On Thu, Jun 3, 2021 at 3:54 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:

>
> Didn't stumble on that one, but will do.
>
> On Thu, 2021-06-03 at 15:40 +0100, Luke Kenneth Casson Leighton wrote:
> > Jean-Paul apologies can you also add name conversion for "ref" to "ref_v"
> > just like "out" / "out_v" it turns out "ref" is a Verilog keyword.
> >
> > l.
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