[Libre-soc-dev] Unexpected clock connexions.

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Sat Jun 5 14:21:09 BST 2021


On Sat, 2021-06-05 at 13:52 +0100, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> > > i am however experimenting tracking down the right H-Tree clock for use
> > 
> > in
> > > ls180Conf, it's probably
> > > 
> > >     ls180Conf.useHTree('por_clk)
> > > 
> > > not
> > > 
> > >     ls180Conf.useHTree('core.por_clk')
> > 
> >   Nono. That's correct. It is really 'core.por_clk'.
> > 
> 
> ok - except this is not a signal that exists.  also it is not helping that
> there is
> a component (test_issuer.ti.core) named "core", however as that is further
> down the hierarchy it's not encountered, here, with this search.

  The search is unambiguous. It means 'core' instance of 'corona' model.
  It doesn't try to match *a* 'core' instance down the hierarchy.

  The meaning of 'core' may be ambiguous, but it is difficult to choose
  someting to would fit everybody's personal preferences..


> >     "representative" at corona level, we must reach it through
> >     the path : 'core.por_clk' (path rooted in corona model,
> >     one instance 'core', which is the ls180).
> > 
> 
> doesn't exist.  you *might* mean pllclk_clk, which is the output
> from the PLL

  Mmmm. Yes it does. 'pllclk_clk' is a signal of 'test_issuer' which
  is connected, in the 'ls180' model to 'por_clk'. So, as we must
  use the representative of net the highest in the hierarchy,
  'core.por_clk'.

  Or is there a mistake in the connexions ?


> > also, is it likely that "coresync_rst" also has to be added?
> > 
> >   Depends. It is in the "middle range". Many sinks, but maybe
> >   not that much to need an H-Tree. If it needs a low skew, maybe.
> > 
> 
> it might be possible to get away with running a reset and set the
> processor to "STOP" mode.
> 
> wait for a bit...
> 
> then bring the processor out of "STOP" mode.
> 
> i think this is what all JTAG unit tests do anyway.
> 
> as long as the processor is held in "STOP" whilst reset is being
> run, it'll be fine.

  OK. So no H-Tree.

-- 

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33) 01.44.27.53.99              
     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip


More information about the Libre-soc-dev mailing list