[Libre-soc-dev] Unexpected clock connexions.

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 3 16:35:17 BST 2021

On Thu, Jun 3, 2021 at 4:33 PM Staf Verhaegen (FibraServi) <
staf at fibraservi.eu> wrote:

> Why not ? I don't see difference between sys_clk coming from IO or
> actually from PLL. JTAG has it's own clock signal.

i don't know, and there is *not enough time to investigate without risk*.

therefore, decision has been made: cut the PLL to JTAG, DMI and Core.


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