[Libre-soc-dev] Unexpected clock connexions.

[Staf Verhaegen (FibraServi)]

On 3/06/2021 17:31, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
>
> On Thu, Jun 3, 2021 at 4:26 PM Staf Verhaegen (FibraServi) <
> staf at fibraservi.eu> wrote:
>
>
>> What I propose is:
>>
>>    * rename the sys_clk IO pin to ref_clk
>>    * connect this ref_clk to PLL input clock signal
>>    * connnect clk_pll output clock to sys_clk.
>>
> this is not a problem.  the problem is that JTAG and DMI do not function
> when this proposal is done.
Why not ? I don't see difference between sys_clk coming from IO or 
actually from PLL. JTAG has it's own clock signal.
Staf.

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