[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Thu, Jun 3, 2021 at 4:26 PM Staf Verhaegen (FibraServi) <
staf at fibraservi.eu> wrote:


> What I propose is:
>
>   * rename the sys_clk IO pin to ref_clk
>   * connect this ref_clk to PLL input clock signal
>   * connnect clk_pll output clock to sys_clk.
>

this is not a problem.  the problem is that JTAG and DMI do not function
when this proposal is done.

therefore we *MUST NOT* attempt it.

Jean-Paul please *DO NOT *attempt to hand-edit the VHDL to try to connect
the JTAG, DMI or Core to different clocks internally.

i have a tested codepath where the Core, JTAG and DMI are confirmed
function *if the sys_clk is connected to all three*.

when the PLL clock is attempted to be connected to JTAG and DMI *all tests
fail*.

l.