[Libre-soc-dev] Unexpected clock connexions.

Staf Verhaegen (FibraServi) staf at fibraservi.eu
Thu Jun 3 16:26:05 BST 2021

On 3/06/2021 17:21, Luke Kenneth Casson Leighton wrote:
> On Thu, Jun 3, 2021 at 4:18 PM Staf Verhaegen (FibraServi) <
> staf at fibraservi.eu> wrote:
>> On 3/06/2021 17:10, Luke Kenneth Casson Leighton wrote:
>>> 300 mhz driving external pin.  also not enough time.  this idea involves
>>> adding an extra pin.  that changes the number of pins.  that change is
>>> required in about 4 places.
>> Why does sys_clk have to be an IO pin ?
> getting confused.  can't focus on this Staf.  adding extra pins too complex.
> adding extra clocks also too complex.

What I propose is:

  * rename the sys_clk IO pin to ref_clk
  * connect this ref_clk to PLL input clock signal
  * connnect clk_pll output clock to sys_clk.

No extra IO pins needed.


Chips want to be free.

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