[Libre-soc-dev] Unexpected clock connexions.

[Jean-Paul Chaput]

On Thu, 2021-06-03 at 17:06 +0200, Staf Verhaegen (FibraServi) wrote:
> 	Error verifying signature: Cannot verify message signature: Incorrect message
> format
> On 3/06/2021 16:18, Luke Kenneth Casson Leighton wrote:
> > Jean-Paul i am having difficulty getting the domains synchronised with
> > nmigen under time pressure.
> > 
> > i am recommending we *BYPASS* the PLL_OUT (coresync_clk) and connect
> > SYS_CLK *DIRECTLY* to TestIssuer and DMI/JTAG.
> 
> Can't you define the PLL input clock as pll_clk_in (or ref_clk) and then connect
> pll_clk to sys_clk and let pll_clk_in (or ref_clk) come from IO ?
> If at all possible I would like to use the PLL for clocking ls180.

  Given the time constraints, I will directly patch the VHDL generated
  files after Yosys+blif2vst. As such, isolating the PLL *or* reconnecting
  everything to the PLL clock output will, I think, give the same amount
  of work. We just have to decide quickly.

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