[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

On Thu, Jun 3, 2021 at 4:21 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:

>
>   Given the time constraints, I will directly patch the VHDL generated
>   files after Yosys+blif2vst.


please do not do that

As such, isolating the PLL *or* reconnecting
>   everything to the PLL clock output will, I think, give the same amount
>   of work. We just have to decide quickly.
>

i really do not recommend doing any manual hand-editing.

please leave sys_clk connected to TestIssuer do not add extra pins
do not add extra clock lines do not add extra clock trees.

pll_clk_out is internally NC, there is the pll test_out which can be
used to verify that the PLL is functional.

we need to minimise changes and minimise risk.

manual editing introduces risk

l.