[Libre-soc-dev] Unexpected clock connexions.

Staf Verhaegen (FibraServi) staf at fibraservi.eu
Thu Jun 3 16:06:33 BST 2021

On 3/06/2021 16:18, Luke Kenneth Casson Leighton wrote:
> Jean-Paul i am having difficulty getting the domains synchronised with
> nmigen under time pressure.
> i am recommending we *BYPASS* the PLL_OUT (coresync_clk) and connect
> SYS_CLK *DIRECTLY* to TestIssuer and DMI/JTAG.

Can't you define the PLL input clock as pll_clk_in (or ref_clk) and then connect pll_clk to sys_clk and let pll_clk_in (or ref_clk) come from IO ?
If at all possible I would like to use the PLL for clocking ls180.


Chips want to be free.

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