[Libre-soc-dev] Unexpected clock connexions.

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 3 16:10:03 BST 2021

On Thu, Jun 3, 2021 at 4:06 PM Staf Verhaegen (FibraServi) <
staf at fibraservi.eu> wrote:

> Can't you define the PLL input clock as pll_clk_in (or ref_clk) and then
> connect pll_clk to sys_clk and let pll_clk_in (or ref_clk) come from IO ?

300 mhz driving external pin.  also not enough time.  this idea involves
adding an extra pin.  that changes the number of pins.  that change is
required in about 4 places.

If at all possible I would like to use the PLL for clocking ls180.

likewise - but we are running out of time.  it is also an untested
codepath.  nmigen DomainRenamer is giving me grief, there is not enough
time to investigate.


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