[Libre-soc-dev] Unexpected clock connexions.

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jun 3 15:18:13 BST 2021

Jean-Paul i am having difficulty getting the domains synchronised with
nmigen under time pressure.

i am recommending we *BYPASS* the PLL_OUT (coresync_clk) and connect
SYS_CLK *DIRECTLY* to TestIssuer and DMI/JTAG.

this is *NOT* the same as *REMOVING* the PLL entirely (repeat: we *KEEP*
the PLL, it is just not connected to TI/DMI/JTAG).

the PLL will still be present and will still output the test signal to be
able to confirm if it is operational.

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