[Libre-soc-dev] Unexpected clock connexions.

[Jean-Paul Chaput]

On Thu, 2021-06-03 at 14:44 +0100, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> 
> On Thu, Jun 3, 2021 at 2:33 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> wrote:
> 
> > 
> > Ha. You may have got a wrong impression about clock tree & H-Tree due
> > to a trick I used to cut corners.
> > 
> 
> probably :)
> 
> 
> > 
> > For the clock signals, do I read correctly that some components with
> > run at *external* clock speed (DEBUG & DMI) ?
> 
> 
> NO. Debug-DMI and JTAG run at the *PLL* clock.

  OK. That is simpler. So all clock at PLL speed.

> but they **GENERATE** the RESET signal that is used by the REST of
> TestIssuer.

> hence why i asked if the debug reset out should be an H-Tree (of some kind)

  H-Tree may be good as I assume it will be used by every DFF on the chip.

> i will draw it as a diagram.
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