[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Jun 3 14:55:59 BST 2021
* all parts of TestIssuerInternal run at PLL CLOCK
* SYS_RST goes **IN** to DMI/JTAG
* DBG_RST comes **OUT* of DMI/JTAG and goes **IN** to ALL other parts of
if this is not done we cannot properly run unit tests, the only way to
reset the core
will be via a hard reset, which will hard reset even the DEBUG interface.
the DEBUG interface is the *ONLY WAY* to upload to the SRAM and DFF memory.
a hard reset would overwrite that and we cannot use JTAG to upload programs.
if we cannot upload programs *we cannot test the core*.
so it is pretty much essential: whereas having the Core and other components
run at PLL_CLK is *not essential*.
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