[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

On Thu, Jun 3, 2021 at 11:07 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:


> But, it's not the case. Some of the DFFs and all the SRAM are directly
> driven
> by the clock I/O pad (~ 6K DFFs).
>
> So, first question is : was it intended ?
>

the SRAM? definitely not.

damnit, i know what's going on there: the core *only* was set in the PLL's
clock domain.

i'll have to reorganise that including reset.

leave it with me.

l.