[Libre-soc-dev] Unexpected clock connexions.

[Luke Kenneth Casson Leighton]

rrright.

* debug DMI and JTAG need to run at PLL clock but use *GLOBAL EXTERNAL
RESET*
* all parts of TestIssuerInternal EXCEPT debug and DMI need to run at PLL
clock and
  have a RESET that is *DRIVEN BY debug DMI* (which, in turn, is driven by
JTAG)
* TestIssuer is combinatorial and simply contains PLL and
TestIssuerInternal.

the reason why Debug / JTAG drives the TestIssuerInternal RESET signal
should
be obvious / clear: the processor and all components needs to be resettable
over
JTAG.

therefore, i imagine, it is not sys_rst that must be an H-Tree, it is the
Debug DMI
reset_output signal that must be an H-Tree.

summary again:

* TestIssuer runs at sys_clk, receives sys_rst
    - sends sys_clk to PLL, receives coresync_clk_o
    - sends coresync_clk_o to TestIssuerInternal
    - sends sys_rst to TestIssuerInternal

* TestIssuerInternal receives sys_rst and coresync_clk_o
    - sends coresync_clk_o to ALL components
    - sends sys_rst to JTAG and Debug/DMI
    - RECEIVES reset_output from Debug / DMI
    - SENDS reset_output to all components (SRAM, Core)

Jean-Paul: is this practical?

if not, then i will *DISABLE* DMI/JTAG reset - which will be a damn
nuisance - the only
way to reset the processor will be a hard external sys_rst line.

l.