[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Jun 3 13:47:12 BST 2021
* debug DMI and JTAG need to run at PLL clock but use *GLOBAL EXTERNAL
* all parts of TestIssuerInternal EXCEPT debug and DMI need to run at PLL
have a RESET that is *DRIVEN BY debug DMI* (which, in turn, is driven by
* TestIssuer is combinatorial and simply contains PLL and
the reason why Debug / JTAG drives the TestIssuerInternal RESET signal
be obvious / clear: the processor and all components needs to be resettable
therefore, i imagine, it is not sys_rst that must be an H-Tree, it is the
reset_output signal that must be an H-Tree.
* TestIssuer runs at sys_clk, receives sys_rst
- sends sys_clk to PLL, receives coresync_clk_o
- sends coresync_clk_o to TestIssuerInternal
- sends sys_rst to TestIssuerInternal
* TestIssuerInternal receives sys_rst and coresync_clk_o
- sends coresync_clk_o to ALL components
- sends sys_rst to JTAG and Debug/DMI
- RECEIVES reset_output from Debug / DMI
- SENDS reset_output to all components (SRAM, Core)
Jean-Paul: is this practical?
if not, then i will *DISABLE* DMI/JTAG reset - which will be a damn
nuisance - the only
way to reset the processor will be a hard external sys_rst line.
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