[Libre-soc-dev] Unexpected clock connexions.

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Thu Jun 3 11:02:41 BST 2021

Hello All,

Now that I solved the bug that prevented me for seeing the result after
correct PLL clock connexion. I can see some strange things (at least to me).

My basic understanding was that the I/O pad clock signal was going straight
to the PLL, where it is multiplied (or passed through, according to selection),
then *all DFF & SRAM* where driven by the clock coming out from the PLL.

But, it's not the case. Some of the DFFs and all the SRAM are directly driven
by the clock I/O pad (~ 6K DFFs).

So, first question is : was it intended ?

If yes, we urgently need to discuss it because I see lot of problems in
having two clocks in the design.

If no, we need to know if it's the Verilog input file which is incorrect
or Yosys + blif2vst that drives something wrong. I already checked the
generated VST, the clock is already split at this level. Before digging
into the blif file, I would like to know if it also present in it.


      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33)              
     ^^ ^^    cell:   home:

    U P M C   Universite Pierre & Marie Curie
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