[Libre-soc-dev] Attempting to run sim error

[Luke Kenneth Casson Leighton]

On Thu, Sep 24, 2020 at 9:09 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Thu, Sep 24, 2020, 12:55 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Thu, Sep 24, 2020 at 8:20 PM Cole Poirier <colepoirier at gmail.com>
> > wrote:
> > > Aha! Thank you. Working on gtkwave debugging of icache.py, and
> > > comparing with icache.vhdl... It turns out the main state machine was
> > > incorrectly indented one level too far in icache_miss()
> >
> > yeah took me about 5 passes through dcache.py / dcache.vhdl to spot
> > things like that.  it's laborious and tedious, needs a lot of
> > patience.
> >
>
> Reasons why {} languages (like Rust) are better :)

yyeah, they tend to get abused, with massive blocks of code that run
on for pages and pages, with no hope of understanding it at a high
level, at a glance.

it's generally good practice to keep everything on one page (where
practical) by calling functions that do sub-work.

unfortunately, the VHDL code being converted in this case is a
maaaaassive 300+ - line FSM.

i broke dcache's FSM down into obvious functions which at least "only"
requires 2 pages to fit the whole FSM.  which is quite important, for
being able to understand the code.  i would prefer it be one page, but
that's not practical here: it's a big FSM.

l.