[Libre-soc-dev] Attempting to run sim error

[Jacob Lifshay]

On Thu, Sep 24, 2020, 12:55 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Sep 24, 2020 at 8:20 PM Cole Poirier <colepoirier at gmail.com>
> wrote:
> > Aha! Thank you. Working on gtkwave debugging of icache.py, and
> > comparing with icache.vhdl... It turns out the main state machine was
> > incorrectly indented one level too far in icache_miss()
>
> yeah took me about 5 passes through dcache.py / dcache.vhdl to spot
> things like that.  it's laborious and tedious, needs a lot of
> patience.
>

Reasons why {} languages (like Rust) are better :)

Jacob