[Libre-soc-dev] daily kan-ban update 08sep2020

[Luke Kenneth Casson Leighton]

On Tue, Sep 8, 2020 at 8:33 PM <whygee at f-cpu.org> wrote:

> CDC6600s were hand-wired in 3D but our chips are limited to 2D (2.5D
> with
> the metal layers). It made sense for a CDC6600 to have all the bits
> decoded
> and taken directly to the units, because transistors were expensive.
> Today, routing is a major bottleneck, particularly at that scale...

yehyeh.

to give you some idea: in the TRAP pipeline there's 4x 64-bit regs in,
and 5x 64-bit regs out.  that's 576 wires already, and adding another
130+ for a fanned-out opcode *and* another 30 for the Comp Unit
Management (GO/REQ), it's just too much.

well, the reorg seems to have been successful.  i also managed to
prune the tree (it's a recursive algorithm) where any empty switch
statements are not included by the parent.  if they were, it would
result in unnecessary PMUX logic.

l.