[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Sep 3 20:44:25 BST 2020


On Thursday, September 3, 2020, Samuel Falvo II <sam.falvo at gmail.com> wrote:

> Just to confirm my understanding of the scope of the project, this is
> a Libre-SOC Power9 core with scoreboards and such?


and multi-issue, yes.

then on top of that, a vector "hardware loop" system that throws multiple
instructions at the multi-issue engine.

it'll be about... 8 months before we get to that point.

l.



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