[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot

[Samuel Falvo II]

Just to confirm my understanding of the scope of the project, this is
a Libre-SOC Power9 core with scoreboards and such?

On Thu, Sep 3, 2020 at 10:02 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Thu, Sep 3, 2020, 09:46 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Thursday, September 3, 2020, Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> > > You really should use a screen capture program -- none of the text on
> > > screen in the video was possible to read even when set to the highest
> > > resolution
> >
> >
> > ironically the capture would be identical to the sim.py run a few weeks
> > ago.
> >
> > the reason for the video is to show the FPGA board behind the laptop.
> > screen capture can't include that. (doh)
> >
>
> video can be edited to switch between screen capture and camera :)
> alternatively, the terminal font size can be temporarily increased to make
> it legible. In any case, thanks for the neat demo!
>
> Jacob
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-- 
Samuel A. Falvo II