[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

[Cole Poirier]

On Thu, Oct 15, 2020 at 10:44 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> litex peripherals understand interrupts.
>
> litex peripheral interconnect understands interrupts.
>
> litex core interconnect understands interrupts.
>
> litex *BIOS* firmware source code know ****-all about
> POWER9/Microwatt/LibreSOC XICS interrupt controllers.

Ok thank you, I think I now understand enough to ask my real questions:
a) Do we need litex *BIOS* firmware source code know about
POWER9/Microwatt/LibreSOC XICS interrupt controllers?
b) If so, how do we make litex *BIOS* firmware source code know about
POWER9/Microwatt/LibreSOC XICS interrupt controllers?


> > Is xics.bin from microwatt?
>
> yes.
>
> > I can't find any reference to xics in the
> > soc repo other than interrupts/xics.py. If xics.bin is from microwatt,
> > how would that help us? And finally, how do I run xics.bin on the
> > fpga?
>
> start with sim.py and you have to enable testgpio and xics in issuer_verilog.py
>
> there is a problem with litex at the moment for FPGAs.

Very helpful. Thank you.

> > Can't you only program the fpga with *.svf and *.bit files?
>
> can you please do less questions per message i'm not able to keep up.

Apologies, I'll make an effort to do so going forwards.

Cole