[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

[Luke Kenneth Casson Leighton]

On 10/15/20, Cole Poirier <colepoirier at gmail.com> wrote:
> On Thu, Oct 15, 2020 at 10:44 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
>>
>> litex peripherals understand interrupts.
>>
>> litex peripheral interconnect understands interrupts.
>>
>> litex core interconnect understands interrupts.
>>
>> litex *BIOS* firmware source code know ****-all about
>> POWER9/Microwatt/LibreSOC XICS interrupt controllers.
>
> Ok thank you, I think I now understand enough to ask my real questions:
> a) Do we need litex *BIOS* firmware source code know about
> POWER9/Microwatt/LibreSOC XICS interrupt controllers?

yes if we want to know if interrupts work in the FPGA.

> b) If so, how do we make litex *BIOS* firmware source code know about
> POWER9/Microwatt/LibreSOC XICS interrupt controllers?

somebody writes the code, in c and assembler, and then writes device
drivers, again in c, that use it.

this is a lot of work (1 week +)


given that xics.bin in microwatt has all of this it is an easier test.

l.