[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

[Luke Kenneth Casson Leighton]

On 10/15/20, Cole Poirier <colepoirier at gmail.com> wrote:

>
> So, litex being the software that hasn't been written to deal with
> these interrupts(?), needs to be modified to be able to handle
> interrupts?

litex peripherals understand interrupts.

litex peripheral interconnect understands interrupts.

litex core interconnect understands interrupts.

litex *BIOS* firmware source code know ****-all about
POWER9/Microwatt/LibreSOC XICS interrupt controllers.


> Is this separate from, but related to the JTAG TAP pins
> needing to be set up for both ulx3s and versa_ep5 fpga's?

absolutely nothing to do with JTAG whatsoever.

>> try to run the microwatt xics.bin test in the fpga.
>
> That's your plan for the workaround? or are you instructing me to do
> this? I'll try it!

:)

> Is xics.bin from microwatt?

yes.

> I can't find any reference to xics in the
> soc repo other than interrupts/xics.py. If xics.bin is from microwatt,
> how would that help us? And finally, how do I run xics.bin on the
> fpga?

start with sim.py and you have to enable testgpio and xics in issuer_verilog.py

there is a problem with litex at the moment for FPGAs.

> Can't you only program the fpga with *.svf and *.bit files?

can you please do less questions per message i'm not able to keep up.

l.