[Libre-soc-dev] versa_ecp5.py P&R failure was daily kan-ban update 14oct2020

[Cole Poirier]

Hi Luke,

Wanted to follow up on this from yesterday cause there's some key
things I don't understand.

> On Wed, Oct 14, 2020 at 12:40 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
>
> not litex's problem / issue.  or it is, sort-of.
>
> interrupts are handled by a generic "signal" that gets allocated to
> litex peripherals on a per-bit basis.
>
> however just raising an interrupt means that, well, duh, the core will
> be interrupted.
>
> and if the software has not been written *to* deal with that
> interrupt, then guess what happens?
>
> so this is why it is and is not litex's problem

So, litex being the software that hasn't been written to deal with
these interrupts(?), needs to be modified to be able to handle
interrupts? Is this separate from, but related to the JTAG TAP pins
needing to be set up for both ulx3s and versa_ep5 fpga's?

> try to run the microwatt xics.bin test in the fpga.

That's your plan for the workaround? or are you instructing me to do
this? I'll try it!

Is xics.bin from microwatt? I can't find any reference to xics in the
soc repo other than interrupts/xics.py. If xics.bin is from microwatt,
how would that help us? And finally, how do I run xics.bin on the
fpga? Can't you only program the fpga with *.svf and *.bit files?

Cole