[Libre-soc-dev] efficient decoding algorithm for variable-length instructions

[Jacob Lifshay]

On Thu, Nov 26, 2020, 12:32 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> my biggest concern is that, knowing how long it's going to take, and
> knowing *in advance* that a single EXTNNN *does not have enough bits*
> to do *one* of P48 or P64, let alone share them all.
>

I never said put all 48 and 64-bit instructions in the same PO (Primary
Opcode), 48-bit instructions are in 1/2 of PO 0 (the other half is 32-bit)
and SVP64 is in 1/2 (or less if we don't need it) of PO 1, shared with the
Power v3.1 64-bit instructions.

>
Some preliminary calculations show that, even assuming we can only use 1/4
(? have to double check -- I know about 1/2 is available) of PO 1 (uses 8
bits for opcode, leaving us 24-bits to play with), and assuming the 32-bit
suffix is completely unmodified, we still have plenty of space:
(ignoring load/store ops for now)

Instructions with 4 reg fields:
(2 bits for register field extension + 1 bit for vector/scalar) * 4 regs
 + 2 bits for elwidth
 + 2 bits for subvector length
 + 3 bits for predication (sufficient for both CR and int reg predicate
schemes)
= 19 bits

Instructions with 3 reg fields:
(2 bits for register field extension + 1 bit for vector/scalar) * 3 regs
 + 2 bits for elwidth
 + 2 bits for subvector length
 + 3 bits for predication (sufficient for both CR and int reg predicate
schemes)
 + 8 bits for small swizzle on 1 reg
= 24 bits

Instructions with 2 reg fields and twin predication:
(2 bits for register field extension + 1 bit for vector/scalar) * 2 regs
 + 2 bits for elwidth
 + 2 bits for subvector length
 + 3 bits for predication (sufficient for both CR and int reg predicate
schemes)
 + 3 bits for predication
 + 8 bits for small swizzle on 1 reg
= 24 bits

Instructions with 2 reg fields and wide swizzle:
(2 bits for register field extension + 1 bit for vector/scalar) * 2 regs
 + 2 bits for elwidth
 + 2 bits for subvector length
 + 3 bits for predication (sufficient for both CR and int reg predicate
schemes)
 + 11 bits for wide swizzle on 1 reg (only 6^4 combinations for 4 elements
that can be one of xyzw01 -- 6^4 = 1296 < 2^11)
= 24 bits

Remember that SVP48 and SVP32 are compressed versions where we just put the
most common SVP64 ops, so we can fit them in PO 0 since we don't need all
ops to be supported.

Jacob

>