[Libre-soc-dev] [OpenPOWER-HDL-Cores] bug in libre-soc "modsd" and possibly in microwatt as well
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Aug 23 13:28:22 BST 2020
On Sun, Aug 23, 2020 at 12:51 PM Paul Mackerras <paulus at ozlabs.org> wrote:
> On Sat, Aug 22, 2020 at 02:20:51PM +0100, Luke Kenneth Casson Leighton wrote:
> > 103dc: 12 06 3b 7e modsd r17,r27,r0
> >
> > the full dump can be found with the following command:
> > lkcl at fizzy:~/src/libresoc/microwatt/tests$
> > powerpc64le-linux-gnu-objdump --disassemble-zeroes -m powerpc -D -b
> > binary -EL 1.bin > 1.dump
> >
> > the results are as follows:
> >
> > * our program instruction analyzer returns 0x7f
> > * microwatt seems to return 0x1 (although there is "delay" in
> > single-stepping which is causing problems)
>
> I looked through the log of a simulation of microwatt running 1.bin.
> I see a value of 0x7fffffff in r0 at that instruction, not 0xff. (In
> fact the 0x7fffffff is the value initially loaded into r0 at the
> beginning of the instruction sequence.)
eh, moo? ahh darn-it, i'm running the binaries under litex. not the
ghdl method, as it's problematic to build ("error 2008 ieee libraries
not found"), and the pipelining results in latency making the log
files hard to interpret and harder to do machine-driven programmatic
cycle-accurate analysis. if a "single-step" mode was added, along
with a DMI regdump was added (see sim.py, below) then it would be
possible to use.
the different run method could be interfering (some difference in
memory or memory accessing, although i don't see how given that the
binary 1.bin is loaded as a litex "integrated SRAM")
> 0x7fffffffffffffff mod 0x7fffffff is 1, which would be why microwatt
> is putting 1 into r17.
ok so hm, leaving aside that the difference (running under litex)
could be interefering, here's the register dump for the two
instructions. clearly r0 is not being reported as 0x7fffffff (it's
0xff), yet the answer (r17=1) is correct!
something very odd is going on. can i ask you a favour of running this:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/sim.py;hb=HEAD
./sim --debug --cpu=microwatt
the verilog file (microwatt.v) and microwatt/core.py is present in
that repository already, and it is - should be - "self-contained" as
long as litex is (obviously) installed. by that i mean: you should
not need to set up libre-soc build dependencies (unless attempting to
run ./sim --cpu=libresoc).
pc : 00000000000103dc
gpr: 00000000000000ff <--- r0 here is not 0x7ffffffff
gpr: 000000000000003f
gpr: ff00ff00ff00ff00
gpr: 00ff00ff00ff00ff
gpr: 000000000001c020
gpr: 000000000000000c
gpr: 0000000000000000
gpr: 022ed98c4f63acd9
gpr: 000000000001c020
gpr: 8888888888000888
gpr: 7fffffffd505ffff
gpr: 000000000000007f
gpr: 8987898789878988
gpr: 1111111111111111
gpr: 8888888888888888 <--- r14
gpr: ffffffffffffffff
gpr: 7fffffffffffffff
gpr: 0000000000000001 <--- r 17
gpr: 00ff00ff00ff00ff
gpr: 00000000ffff8000
gpr: 7f6e5d4c3b2a1908
gpr: ffffffffffffffff
gpr: 00000000ffff8000
gpr: 0000000000000000
gpr: 0000000000000000
gpr: ff00ff005bf7ff00
gpr: 8888888888000887
gpr: 7fffffffffffffff <--- r27
gpr: 000000000001c01f
gpr: 0000000000000000
gpr: ffffffffffffffff
gpr: 00000000000000ff
pc : 00000000000103e0
gpr: 00000000000000ff
gpr: 000000000000003f
gpr: ff00ff00ff00ff00
gpr: 00ff00ff00ff00ff
gpr: 000000000001c020
gpr: 000000000000000c
gpr: 0000000000000000
gpr: 022ed98c4f63acd9
gpr: 000000000001c020
gpr: 8888888888000888
gpr: 7fffffffd505ffff
gpr: 000000000000007f
gpr: 8987898789878988
gpr: 1111111111111111
gpr: 000000000001c020
gpr: ffffffffffffffff
gpr: 7fffffffffffffff
gpr: 0000000000000001 <-- r17
gpr: 00ff00ff00ff00ff
gpr: 00000000ffff8000
gpr: 7f6e5d4c3b2a1908
gpr: ffffffffffffffff
gpr: 00000000ffff8000
gpr: 0000000000000000
gpr: 0000000000000000
gpr: ff00ff005bf7ff00
gpr: 8888888888000887
gpr: 7fffffffffffffff <- r27
gpr: 000000000001c01f
gpr: 0000000000000000
gpr: ffffffffffffffff
gpr: 00000000000000ff
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