[Libre-soc-bugs] [Bug 1044] SVP64 implementation of pow(x,y,z)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Oct 10 10:37:29 BST 2023


--- Comment #51 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to djac from comment #50)

> Beyond a cursory look at what the hardware approach might be it is not
> efficient to second guess the hardware implementation until RED has a
> hardware team which can interact on these ideas.

not just inefficient but actually damaging because they will not
have any examples to demonstrate why *their* misunderstandings of
the full features are wrong (yes, the hardware team will have to learn
SVP64 "on-the-hoof").

we *need* examples that push the hardware implementors out of their
SIMD-based assumptions.

> Dont loose anything clever but as I have said before save them for when
> future thinking.

yes, this is part of an ISA Designer's responsibility to think
through *all* possible implementations (exactly like how the
Khronos Group Members must do).

as the person directly responsible for SVP64 and having been on it
100% full-time i had to do this (partly in my head, partly written).
it will be years if not decades before all "hardware tricks" emerge.

a SIMD ISA on the other hand, the only real "tricks" that they can
apply are:

1. multi-issue (both ARM NEON and IBM POWER9/10 do this)

2. Cray-conceptualised vector chaining *on elements in the SIMD registers*
   ( the only public recent company to reveal they did this
   was AMD with their AVX512 implementation.)

we have way more options open than just those two, thanks to the
clean "abstracted" API, but i say "we" when i mean *all* future
implementors of SVP64 (not just RED, in the distant future).

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