[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 29 12:11:05 BST 2023


--- Comment #18 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
It is not obvious in what format 'writeregs' and 'readregs' are supposed to be.
Are 'get_input_regs()' and 'get_output_regs()' supposed to produce a set of
Hazard objects (with actions 'r' and 'w' respectively)?

I ask this because on line #216, you're using the 'difference_update' method,
which is part of a set() object.

Also, Fetch's 'process_instructions()' has to be run twice initially. First to
store the trace into stages[0], and then again for stages[0] to propagate to
the Decode (via add_instruction). I'm assuming this is expected behaviour
because fetch and decode of the same instruction cannot happen at the same

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