[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 28 21:43:42 BST 2023


--- Comment #17 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Looked at the inorder.py code today. 

Started adding code for decode stage to determine read/write registers.

If this is not at all appropriate, I'll stop working on it.

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