[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #17 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Looked at the inorder.py code today. 

Started adding code for decode stage to determine read/write registers.
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=2a35755d34df6aedb05eac2287fcd2913c6ac957

If this is not at all appropriate, I'll stop working on it.

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