[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1072

--- Comment #39 from Jacob Lifshay <programmerjake at gmail.com> ---
https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=bd6445153bf9ad2d571fcfc84533eb5709769226

commit bd6445153bf9ad2d571fcfc84533eb5709769226
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue May 23 20:10:58 2023 -0700

    test fcvttgo. with traps enabled

commit 7145327b2fd35d35aaf2510cae6fb3ad22488811
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue May 23 20:10:18 2023 -0700

    ISACaller: generate FP trap

commit aa2ae1dcae0470f15e3a65320f68826930e43f34
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue May 23 19:34:15 2023 -0700

    test fcvttgo. with VE=1 too

commit d18a4294ce0687838133c00b4f4778c1430366b6
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue May 23 19:33:01 2023 -0700

    fcvttg[s][o][.] needs EXTRA_UNINIT_REGS: RT

commit 870f7f23273d1d0d49af9ed09d82c42f2347ef07
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue May 23 19:24:34 2023 -0700

    add support for adding extra uninit_regs from html comment

    I chose an html comment since it's not part of the proposed pseudocode

    like so:
    * blah RT,RA
    Pseudo-code:

    <!-- EXTRA_UNINIT_REGS: RT -->
        if rand() then
            RT <- 42 + (RA)

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