[Libre-soc-bugs] [Bug 1086] ls2 verilator sim - setting up chroot and documentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1086

--- Comment #13 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Andrey Miroshnikov from comment #12)
>
> Calling 'make microwatt-verilator' fails
> %Error: Exiting due to too many errors encountered; --error-limit=50
> 
> The errors that are occuring at to do with the timescale:
> %Error-TIMESCALEMOD: ls2.v:5:8: Timescale missing on this module as other
> modules have it (IEEE 1800-2017 3.14.2.2)

After hunting through the mailing list I found that Tobias went through a
similar experience trying to get ls2 verilator sim working:
https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-April/004778.html
https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-April/004779.html
https://libre-soc.org/irclog/%23libre-soc.2022-04-24.log.html#t2022-04-24T14:23:30

To check, I commented out lines #78-79:
https://git.libre-soc.org/?p=ls2.git;a=blob;f=Makefile;h=a41fe72aae852011623794b808f4db85d6332e5c;hb=426e2d9585cd4b1fb96a38987f97878285ee5ba7

So the verilator command must be failing. Any ideas and/or past experience as
to why it might be failing?

Before the timescalemod errors, there was one warning about a missing pin:
%Warning-PINMISSING: ls2.v:47044:21: Cell has missing pin: 'insn'
47044 |   external_core_top core_top (
      |                     ^~~~~~~~
                     ... Use "/* verilator lint_off PINMISSING */" and lint_on
around source to disable this message.

But this shouldn't be causing the program to stop.

Tobias had not mentioned how he fixed it.

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