[Libre-soc-bugs] [Bug 1086] ls2 verilator sim - setting up chroot and documentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1086

--- Comment #6 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
After running through the setup scripts in the following order (after creating
chroot and copying over the dev scripts):
./install-hdl-apt-reqs
./hdl-dev-repos
./hdl-tools-yosys
./nextpnr-xilinx-install

I was able to make the external Libre-SOC core.

Looking at the log of nextpnr-xilinx-install, I saw that antlr parser was not
present. There's an automatic fallback to textX parser, but I haven't tested
this software (not working on FPGA yet).

After running hdl-dev-ls2, I noticed the following in the log:

- The nmigen got overwritten (was at nmigen 0.1.dev1205+g29dec30, which isn't
good, given that we needed 0.2). An older nmigen version being installed by
hdl-dev-repos was also a problem I encountered back in January:
https://libre-soc.org/irclog/%23libre-soc.2023-01-16.log.html#t2023-01-16T19:16:58

- Pyvcd was overwritten from 0.2.4 to 0.1.7.

>From this point I was also not able to compile the external Libre-SOC core
anymore because of older Pyvcd:
ImportError: cannot import name 'GTKWColor' from 'vcd.gtkw'
(/usr/local/lib/python3.7/dist-packages/pyvcd-0.1.7-py3.7.egg/vcd/gtkw.py)



I uploaded the logs in a tar.gz file (20220521_ls2_scriptlogs.tar.gz) in my
home directory of libre-soc.org (should be readable). I only included the
successful run of make microwatt_external_core.


NOTE: All the scripts were run *UNMODIFIED* (latest git commit
7e125043b8ac0030a47188f85c1e2128f8ae6cec), so you should be able to replicate
this.

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