[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
converted to explicit argument for trace-log-writing

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=140c9b38e3f011ac216ede4b69f25aa9796b93ee

there is no need to focus on ISACaller - at all - for now - until
the inorder.py model has been confirmed with unit tests that it
is reasonably functional.

the inorder.py model as a completely standalone independent program
may be worked on *without* needing a branch because it has absolutely
no connection whatsoever of any kind to any other code.

inorder.py should in no way be modified to import any other code

under no circumstances should any other code be modified to import inorder.py

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