[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this needs to be *brutally* simple.  we have full control over the format
and it is auto-generated.  therefore there is absolutely no need for
any error-checking of any kind, and as it is single-purpose there is
absolutely no need whatsoever for dataclasses, classes, or anything more
complex than lists tuples and dicts.  even namedtuple is a stretch.

most of the work here actually needs to go into the unit tests, and
making sure that the model is "correct", followed by adding in power-estimates
(which will be done later).


https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=365af65074431ccba0483dbd6cf618d135421fd6

added namedtuple for the hazards (nothing more complex needed)

+# trace file entries are lists of these.
+Hazards = namedtuple("Hazards", ["action", "target", "ident", "offs",
"elwid"])

added profiles (as a dict - nothing more complex needed)

+# key: readport, writeport (per clock cycle)
+HazardProfiles = {
+    "GPR": (4, 1),  # GPR allows 4 reads 1 write possible in 1 cycle...
+    "FPR": (3, 1),

added read_file function: nothing more complex needed, no error-checking
required

+def read_file(fname):
+    """reads a trace file in the format "[r:FILE:regnum:offset:width]* # insn"
+    """
+    ...

-- 
You are receiving this mail because:
You are on the CC list for the bug.