[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #12 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I'll wait for CI, because ISACaller is a common code, so I don't want to end up
in a situation when I broke something. Please let me know your opinions and
suggestions; feel free to give this functionality a shot. Here's what I had for
the first three tests in test_caller.py:

$ TRACEFILE=true python3 src/openpower/decoder/isa/test_caller.py | grep
tracefile
tracefile /tmp/trace_test0_iap01fbe.trace (permanent)
tracefile /tmp/trace_test1__ee5vb3b.trace (permanent)
tracefile /tmp/trace_test2_s3xvvg2d.trace (permanent)
$ cat /tmp/trace_test0_iap01fbe.trace 
add 1, 3, 2 rGPR:3.0/64 rGPR:2.0/64 wGPR:1.0/6
$ cat /tmp/trace_test1__ee5vb3b.trace 
addi 3, 0, 0x1234 rGPR:0.0/64 wGPR:3.0/64
addi 2, 0, 0x4321 rGPR:0.0/64 wGPR:2.0/64
add  1, 3, 2 rGPR:3.0/64 rGPR:2.0/64 wGPR:1.0/64
$ cat /tmp/trace_test2_s3xvvg2d.trace 
addi 1, 0, 0x0010 rGPR:0.0/64 wGPR:1.0/64
addi 2, 0, 0x1234 rGPR:0.0/64 wGPR:2.0/64
stw 2, 0(1) rGPR:1.0/64 rGPR:2.0/64
lwz 3, 0(1) rGPR:1.0/64 wGPR:3.0/64

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