[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1072

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #18)
> bit 0 is the first fractional bit, since that is
> what the PowerISA spec expects.

actually bit 0 is the lsb integer bit, bit 1 is the first fractional
bit...adding a todo to fix that.

-- 
You are receiving this mail because:
You are on the CC list for the bug.