[Libre-soc-bugs] [Bug 1072] implement fcvt/fmv instructions in ISACaller (ls006)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1072

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
I added some fmv/fcvt tests, copying some toint32 tests from V8, however I ran
into a roadblock: FPSCR is not implemented -- Luke, can you add that? it seems
likely to be difficult for me since it isn't actually an SPR, it's a completely
custom register.

I also added some misc. validity checking -- checking that fields.txt lines up
correctly and checking that generated .py files aren't missing from .gitignore

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c8b2c5d2c984cc444880187679c2a9589bae0526

commit c8b2c5d2c984cc444880187679c2a9589bae0526
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Thu May 4 19:19:29 2023 -0700

    add initial fmv/fcvt tests, though they're broken due to FPSCR being
unimplemented

commit d953b17515cce377efcf77544d15d3639aa3d974
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Thu May 4 17:55:15 2023 -0700

    add check that generated .py files are in .gitignore

commit 496c01f81a9afda2edca268e93d5f0fa785a220a
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Thu May 4 17:34:27 2023 -0700

    verify fields.txt forms' field separators ('|') line up with headers'

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