[Libre-soc-bugs] [Bug 841] Idea for openpower/x86/aarch64/riscv/etc. programmable decoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=841

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this was the entire basis of Transmeta. they still got sued into oblivion by 
at least Intel. also the DEC Alpha team was bought wholesale by Intel not
for the hardware but for their *software* JIT compiler, which Intel then used
to create exactly what you're describing: CISC-to-RISC *hardware* level
microcoded JIT translation, and patented the s*** out of it.

other than that it's a fantastic idea that keeps coming
up and i have vague recollections that OPF would very much like to see
user-programmable micro-coding become part of the Power ISA.
(caveat: it's a hell of a lot of work).

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