[Libre-soc-bugs] [Bug 841] New: Idea for openpower/x86/aarch64/riscv/etc. programmable decoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=841

            Bug ID: 841
           Summary: Idea for openpower/x86/aarch64/riscv/etc. programmable
                    decoder
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: DEFERRED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: programmerjake at gmail.com
          Reporter: programmerjake at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

writing this down before I forget:
i have an idea for a cpu that can execute any isa by having the decoder be
programmable, so we could build a compiler that takes qemu's source (or
similar) -- probably the guest instruction to tiny-code-gen translator -- and
spits out a binary that programs the decoder to decode that selected
instruction set. (taking qemu's source and using it to program a fully-general
decoder probably would get around patents on the instruction sets, since the
isa vendors presumably are fine with qemu decoding their instruction sets (the
vendors often contribute to qemu), and this is just another way of executing
parts of qemu).

the decoder would be made from 2 parts, a fpga-style pipeline (fast-path) that
decodes several instructions per clock along with a flag for when it needs to
fallback to the slow-path, and a turing-complete slow path that either is a
simple cpu that spits out the decoded instructions or gets the main cpu to
execute the program to decode instructions (via a super-fast interrupt).

the decoded instructions would then go into an uop-cache, so programs can still
generally run quickly even if the instructions used are complex/slow to decode.

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