[Libre-soc-bugs] [Bug 841] Idea for openpower/x86/aarch64/riscv/etc. programmable decoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=841

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> this was the entire basis of Transmeta. they still got sued into oblivion by 
> at least Intel. 

afaict the difference is transmeta's jit translator isn't derived from
something that intel already gave a patent grant for the use of (like in the
apache 2.0 license) where intel has contributed to open source software that
decodes x86 instructions.

by having the binary programmed into our decoder be derived from something
intel already granted patent licenses for (something like qemu), our decoder
benefits from those patent licenses for decoding x86 specifically. that
wouldn't affect the actual decoder hw, which is why that has to not be
x86-specific.

> also the DEC Alpha team was bought wholesale by Intel not
> for the hardware but for their *software* JIT compiler, which Intel then used
> to create exactly what you're describing: CISC-to-RISC *hardware* level
> microcoded JIT translation, and patented the s*** out of it.

iirc they started doing that more than 20yr ago so those patents should be
expired...also intel wasn't the first one to have a programmable decoder with
microcode.

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