[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul Chaput from comment #7)

>   Yes. I will analyse to what block the clocks are connected.
>   See if a manual placement of said block can help.
> 
>   Also will look at the data flow as we have huge buses and
>   clearly bi-directional data-flow.

yes. all IO Pads. these are combinatorial muxes to re-route IO
for testing.

>   Concerning the jtag_tck, that will depend on how many DFFs
>   is it connected to and how widespread in the rest of the
>   design they are.

there will be a lot of Muxes onto the wishbone bus, i set that
to cut off the core in case things go wrong, but they should
not involve DFFs there.

basically, whilst information on the JTAG side comes from or
into ASync DFFs to cross over between tck and sysclk, signal
interception goes through *combinatorial* muxes.

you will see this (Clock-Domain-Crossing)

    jtag side signal -> DFF(tck) -> DFF(clk) -> clk controlled signal


you will NEVER see this:

    jtag side signal -> DFF(clk) -> clk controlled signal

or this:

    jtag side signal -> DFF(tck) -> clk controlled signal


this is something you will also see on eth_mac around the FIFOs, a
pair of DFFs chained together.

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