[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #7 from Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)

> adhoc clock tree, localisation of the parts connected to it?
> be interesting to hear, also it occurs to me that maybe jtag_tck
> could be treated similarly on ls180 as bigger test?

  Yes. I will analyse to what block the clocks are connected.
  See if a manual placement of said block can help.

  Also will look at the data flow as we have huge buses and
  clearly bi-directional data-flow.

  Concerning the jtag_tck, that will depend on how many DFFs
  is it connected to and how widespread in the rest of the
  design they are.

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