[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

Staf Verhaegen <staf at fibraservi.eu> changed:

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                 CC|                            |staf at fibraservi.eu

--- Comment #9 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> 
> also it occurs to me that maybe jtag_tck
> could be treated similarly on ls180 as bigger test?

The jtag_clk is indeed an interesting case as the boundary scan goes over the
whole input signals. So although jtag_tck is not used in the core it needs to
be distributed close to all the IO cells. The placer is also involved here as
that will determine where exactly the logic is placed.

As the boundary scan is basically a big shift register one could also have a
strategy for jtag_clk that distributes jtag in a circular way and not a tree.
Typically this is done with the clock going in the opposite direction of the
shift register to help for hold violations.

>From timing point of view the max. operating frequency for jtag_tck can also be
made lower than the core max. clock frequency.

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