[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #21 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #20)
> (In reply to Staf Verhaegen from comment #19)
> > (In reply to Luke Kenneth Casson Leighton from comment #18)
> > > (In reply to Staf Verhaegen from comment #17)
> > > > I would like to provide simulation model for a dual port SRAM + nmigen
> > > > wrapper for 1WxR blocks.
> > > 
> > > brilliant. this is the 6T cell? (1R-or-1W)? 
> > 
> > No, the dual port SRAM uses an 8T cell.
> 
> ah brilliant so definitely 1R1W, which is fantastic.
> 
> we've found someone who will be happy to give a quote for a 10T Cell (2R1W)
> using FlexLib.  they're a commercial Memory Compiler company who are happy to
> do this as an experiment, and i've encouraged and explained to them the
> benefits of using sky130 MPWs.  i'd very much like them to be able to get
> started from something pre-existing, and get started very soon given the
> time constraints, so it is really important that they have as much source
> code as possible, otherwise they end up duplicating effort
> (and charging for it).
> 
> therefore it's really important to make available the 1RW source code
> the moment it is written (even if it is in a development branch).

Ah nice. The picture changes when people with SRAM design experience are
involved. Problem is that I am overloaded meaning also that I don't have the
bandwidth to teach people without SRAM design experience how to design a SRAM
(block).

I think it is best then that we have a telecom with me and them to see how to
proceed from here. As I am overloaded anyway I would be happy to let the
compiler design be done by third party and deviate considerable part of my NGI
Pointer money to the party. I could then focus on stabilizing the API and make
code base amenable for external contributions. Which ATM is heavily slowed down
by other interfering deadlines.

Unfortunately I think it is either one or the other in the NGI Pointer
timeframe; e.g either I do dual port compiler design or I support other party
in doing a compiler design (type(s) to be chosen) but not both at the same
time.
Actually my preference is the latter as I am frustrated that I always am saying
I will be stabilizing the API but not deliver.

So I will also change plans a little and not focus on the dual port RAM models
but on completing the docs for the sky130 SRAM tape-out I just finished. This
contains the 6T cell design which should be good start for discussion with your
party.

-- 
You are receiving this mail because:
You are on the CC list for the bug.