[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #19)
> (In reply to Luke Kenneth Casson Leighton from comment #18)
> > (In reply to Staf Verhaegen from comment #17)
> > > I would like to provide simulation model for a dual port SRAM + nmigen
> > > wrapper for 1WxR blocks.
> > 
> > brilliant. this is the 6T cell? (1R-or-1W)? 
> 
> No, the dual port SRAM uses an 8T cell.

ah brilliant so definitely 1R1W, which is fantastic.

we've found someone who will be happy to give a quote for a 10T Cell (2R1W)
using FlexLib.  they're a commercial Memory Compiler company who are happy to
do this as an experiment, and i've encouraged and explained to them the
benefits of using sky130 MPWs.  i'd very much like them to be able to get
started from something pre-existing, and get started very soon given the
time constraints, so it is really important that they have as much source
code as possible, otherwise they end up duplicating effort
(and charging for it).

therefore it's really important to make available the 1RW source code
the moment it is written (even if it is in a development branch).


> But before having a more in-depth discussion on that subject I would like to
> have the dual port models available.

ok.  then the fastest way which saves time is for them to be in this
directory: https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/bus;hb=HEAD

that's a catch-all location for things not yet with an appropriate location,
it includes SPBlock512W64B8W.py for example.

> BTW, I do find the '1R-or-1W' name very confusing it's typically called 1RW.

ah i used that term purely because i didn't know the industry-standard one.
now i know it, i'll use 1RW in future.  now i see it written, it makes perfect
sense: the number (1) followed by the actions (RW).


> This is just about the simulation model so without the design of SRAM itself
> which will need a separate task. The latter will be done in the
> [c4m-flexcell repository](https://gitlab.com/Chips4Makers/c4m-flexmem) so
> commits will be done when going along. 

ok great.

> The TSMC 180nm specific layout of
> course can't be made public; the Sky130 will be.

yes, perfectly understood.

> That said, I want to clarify that a SRAM cell is not a digital cell; analog
> design is needed to get a full SRAM block working. 

yes, i heard.  drive-line strength matters when inserted into a matrix;
the size of the 2 transistors in the FF matters: get them wrong and you
can set but not reset, or you can read but not write.

> You can't just write a
> digital wrapper around a SRAM cell to get a SRAM block which seems a wrong
> assumption made in #781.

i believe Cesar was intending to do alternating-clocks at the top level
(the Memory Block) on a *pair* of Memory Blocks.

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