[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #19 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> (In reply to Staf Verhaegen from comment #17)
> > I would like to provide simulation model for a dual port SRAM + nmigen
> > wrapper for 1WxR blocks.
> 
> brilliant. this is the 6T cell? (1R-or-1W)? 

No, the dual port SRAM uses an 8T cell. As said above I do see risks associated
with the proposal in #781 which I feel is not appropriate for the strict
timeline needed for the current project.
But before having a more in-depth discussion on that subject I would like to
have the dual port models available.

BTW, I do find the '1R-or-1W' name very confusing it's typically called 1RW.

> 
> > Is there a good place somewhere in the repos where I can do that ? Or should
> > I provide new repo ?
> 
> a new one is good, i can mirror it.
> 
> btw please do also commit the source code of the cell,
> we cannot operate on a "commit when finalised basis"

This is just about the simulation model so without the design of SRAM itself
which will need a separate task. The latter will be done in the [c4m-flexcell
repository](https://gitlab.com/Chips4Makers/c4m-flexmem) so commits will be
done when going along. The TSMC 180nm specific layout of course can't be made
public; the Sky130 will be.

That said, I want to clarify that a SRAM cell is not a digital cell; analog
design is needed to get a full SRAM block working. You can't just write a
digital wrapper around a SRAM cell to get a SRAM block which seems a wrong
assumption made in #781.

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