[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #17)
> I would like to provide simulation model for a dual port SRAM + nmigen
> wrapper for 1WxR blocks.

brilliant. this is the 6T cell? (1R-or-1W)? 

> Is there a good place somewhere in the repos where I can do that ? Or should
> I provide new repo ?

a new one is good, i can mirror it.

btw please do also commit the source code of the cell,
we cannot operate on a "commit when finalised basis"

if you also include the OSI-approved License which
says (usually) "No warranty, No liability" there is
no risk to you.

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